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ISL97634
Data Sheet March 7, 2008 FN6264.3
White LED Driver with Wide PWM Dimming Range
The ISL97634 represents an efficient and highly integrated PWM boost LED driver that is suitable for 1.8" to 3.5" LCDs that employ 2 to 7 white LEDs for backlighting. With integrated Schottky diode, OVP, and wide range of PWM dimming capability, the ISL97634 provides a simple, reliable, and flexible solution to the backlight designers. The ISL97634 features a wide range of PWM dimming control capability. It allows dimming frequency as low as DC to 32kHz beyond audible spectrum. The ISL97634 also features a feedback disconnect switch to prevent the output from being modulated by the PWM dimming signal that minimizes system disturbance. The ISL97634 is available in the 8 Ld TDFN (2mmx3mm) package. There are 14V, 18V, and 26V OVP options that are suitable for 3 LEDS, 4 LEDs, and 7 LEDs (3.5V/20mA type) backlight applications respectively. The ISL97634 is specified for operation over the -40C to +85C ambient temperature at input voltage from 2.4V to 5.5V.
Features
* Drives Up to 7 LEDs in Series (3.5V/20mA type) * OVP (14V, 18V, and 26V for 3, 4 and 7 LEDs Applications) * PWM Dimming Control From DC to 32kHz * Output Disconnect Switch * Integrated Schottky Diode * 2.4V to 5.5V Input * 85% Efficiency * 1.4MHz Switching Frequency Allows Small LC * 1A Shutdown Current * Internally Compensated * 8 Ld TDFN (2mmx3mm) * Pb-Free (RoHS Compliant)
Applications
* LED Backlighting for: - Cell phones - Smartphones - MP3 - PMP - Automotive Navigation Panel - Portable GPS
Pinout
ISL97634 (8 LD TDFN) TOP VIEW
GND 1 VIN 2 PWM/EN 3 NC 4
8 LX 7 VOUT 6 FBSW 5 FB
Ordering Information
PART NUMBER (Note) ISL97634IRT14Z-T PART MARKING ELE ELE ELF ELF ELG ELG PACKAGE (Pb-free) Tape & Reel 8 Ld 2x3 TDFN 8 Ld 2x3 TDFN 8 Ld 2x3 TDFN 8 Ld 2x3 TDFN 8 Ld 2x3 TDFN 8 Ld 2x3 TDFN PKG. DWG. # L8.2x3A L8.2x3A L8.2x3A L8.2x3A L8.2x3A L8.2x3A
Typical Application Circuit
10H or 22H VIN
ISL97634IRT14Z-TK ISL97634IRT18Z-T ISL97634IRT18Z-TK
VIN PWM/EN NC
LX VOUT
ISL97634IRT26Z-T ISL97634IRT26Z-TK
FBSW FB
GND
*Please refer to TB347 for details on reel specifications NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020..
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006-2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL97634
Absolute Maximum Ratings (TA = +25C)
Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V LX Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V FBSW Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
Thermal Information
Thermal Resistance JA (C/W) JC (C/W) 8 Ld TDFN Package (Notes 1, 2). . . . . 77 12 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed over temperature of -40C to +85C unless otherwise stated. Typ values are for information purposes only at TJ = TC = TA = +25C.
NOTE: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER VIN IIN Supply Voltage Supply Current
VIN = VPWM/EN = 3V CONDITION MIN 2.4 PWM/EN = 3V, enabled, not switching PWM/EN = 0V, disabled 0.8 TYP MAX 5.5 1.5 1 1,300 90 400 ILX = 100mA VLX = 28V 90 VFB = 95mV 10 IDIODE = 100mA, TA = +25C ISL97634IRT14Z ISL97634IRT18Z ISL97634IRT26Z 600 14 18 26 28 0.6 1.5 1.5 200 850 1,450 95 470 900 0.01 95 1 100 1 1,600 UNIT V mA A kHz % mA m A mV A mV V V V V V s s
DESCRIPTION
fSW DMAX ILIM RSW(LX) ILEAK VFB IFB RSW(FBSW) VDIODE OVP
Switching Frequency Maximum Switching Duty Cycle LX Current LX Switch ON-Resistance LX Switch Leakage Current Feedback Voltage FB Pin Bias Current FBSW Switch ON-Resistance Schottky Diode Forward Voltage Overvoltage Protection
VIL VIH PWM_on EN_delay
Logic Low Voltage of PWM/EN Logic High Voltage of PWM/EN Minimum PWM On-Time EN to Vout Delay
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FN6264.3 March 7, 2008
ISL97634 Block Diagram
VIN (2.4V TO 5.5V) CIN VIN PWM/EN L
LX
1.4MHZ OSCILLATOR AND RAMP GENERATOR
ISL97634
VOUT
COUT PWM COMPARATOR PWM LOGIC CONTROLLER FET DRIVER
2 LEDs to 7 LEDS
CURRENT SENSE GND FBSW PWM/EN
GM AMP COMPENSATION
GM AMPLIFIER
FB 95mV BANDGAP REFERENCE GENERATOR RSET
Pin Description
PIN NUMBER 1 2 3 4 5 6 7 8 PIN NAME GND VIN PWM/EN NC FB FBSW VOUT LX Ground Pin. Connect to local ground. Input Supply Pin. Connect to the input supply voltage, the inductor and the input supply decoupling capacitor. PWM or Enable Pin. Connect external PWM signal allows pulse width modulation current operation. Enable signal allows peak current operation or disable signal shuts down the device. No Connect Feedback Pin. Connect the sense resistor between FB and ground. The cathode of bottom LED can also be connected at this pin if the output current is not to be PWMed. FB Disconnect Switch. Connect to the cathode of the bottom LED if the output current to be PWMed. Output Pin. Connect to the anode of the top LED and the output filter capacitor. Switching Pin. Connect to inductor. DESCRIPTION
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ISL97634 Typical Performance Curves
90 85 80 EFFICIENCY (%) 75 3 LEDs, 10H 70 65 60 55 50 3 LEDs, 22H 7 LEDs, 22H ILED_peak = 25mA VIN = 4V RSET = 4 fPWM = 1kHz 0 20 40 60 80 PWM DUTY CYCLE (%) 100 7 LEDs, 10H 4 LEDs, 10H Iq (mA) 0.6 1.0 0.8
0.4
0.2 0.0
-0.2
0
1
2
3 VIN (V)
4
5
6
FIGURE 1. EFFICIENCY vs PWM DUTY CYCLE
FIGURE 2. QUIESCENT CURRENT vs VIN (PWM/EN = HI)
20.08
19.76 19.74
20.04 19.72 IO (mA) IO (mA) 19.70 19.68 19.66 19.64 19.92 19.62
20.00
19.96
0
5
10
15 VOUT (V)
20
25
30
2.5
3.0
3.5
4.0 VIN (V)
4.5
5.0
5.5
FIGURE 3. LOAD REGULATION (VIN = 4V)
FIGURE 4. LINE REGULATION
100 90 80 FB VOLTAGE (mV) 70 60 50 40 PWM/EN 30 20 10 0 0 20 40 60 80 100 120 DUTY CYCLE (%) 32kHz ILED 20kHz 7 LEDs VIN = 4V RSET = 4 L = 10H VOUT 1kHz LX VIN = 4V R1 = 4 L1 = 22H
FIGURE 5. DIMMNG LINEARITY (FB VOLTAGE) vs DUTY CYCLE
FIGURE 6. PWM DIMMING AT 1kHz, D = 1%
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ISL97634
VOUT VOUT LX LX
PWM/EN VIN = 4V ILED R1 = 4 L1 = 22H
PWM/EN
ILED VIN = 4V R1 = 4 L1 = 22H
FIGURE 7. PWM DIMMING AT 1kHz, D = 1% ZOOM IN
FIGURE 8. PWM DIMMING AT 1kHz, D = 99%
VOUT
LX R1 = 4 VIN = 4V L1 = 22H PWM/EN
ILED
FIGURE 9. PWM DIMMING AT 20kHz, D = 50%
Detailed Description
The ISL97634 uses a constant frequency, current mode control scheme to provide excellent line and load regulation. There are three OVP models for driving 3, 4 and 7 LEDs (3.5V/20mA type) and their OVP thresholds are set at 14V, 18V and 26V respectively. The ISL97634 operates from an input voltage of 2.4V to 5.5V and ambient temperature from -40C to +85C. The switching frequency is around 1.45MHz and allows the driver circuit to employ small LC components. The peak forward current of the LED is set using the RSET resistor. In the steady state mode, the LED peak current is given by Equation1:
V FB I LED = -------------R SET (EQ. 1)
pulse width modulated output current. It is well understood that the LED brightness is a linear function of the LED current. In addition, the average LED current corresponds to the duty cycle "D" of the PWM signal as shown in Equation 2:
V FB I LED-AVG = -------------- D R SET (EQ. 2)
PWM Dimming
The ISL97634's PWM/EN pin can be tied permanently to high for a fixed current operation. On the other hand, the ISL97634 can be applied with an external PWM signal to 5
As a result, PWM signal provides a means to dim the LED brightness. PWM dimming offers the best LEDs matching over DC dimming. It is because the LED peak current operating point is far away from the knee of the diode I-V curve where part to part variations are high. The PWM dimming test results are shown in Figure 6 with two PWM frequencies, 1kHz and 20kHz. The vertical scale parameter FB is proportional to the current and therefore the brightness. For the ISL97634, PWM dimming provides linear dimming adjustment with low frequency signal, such as 1kHz and
FN6264.3 March 7, 2008
ISL97634
below. The applied PWM dimming signal can be up to 32kHz; however, the dimming linearity is compromised at low duty cycles as their durations are too short for the ISL97634's control loop to respond properly. This non-ideality behavior does not cause any functional problem. The PWM dimming linear responses in Figure 5 are expanded in Figure 10. At 1kHz PWM dimming, the duty cycle can virtually vary from below 1% to DC. On the other hand, at 20kHz PWM dimming, the linearity range is from 5% to DC only.
10 9 8 FB VOLTAGE (mV) 7 6 5 4 3 20kHz 2 1 32kHz 0 0 2 4 6 8 DUTY CYCLE (%) 10 12 7 LEDs VIN = 4V RSET = 4 L = 10H ILED 1kHz
.
VOUT
LX
PWM/EN VIN = 4V R1 = 4 L1 = 22H
FIGURE 12. PWM DIMMING AT 1kHz WITHOUT USING FBSW
The FBSW should be used for PWM dimming as illustrated in "Typical Application Circuit" on page 1. During the PWM off time, the FBSW is opened. The LEDs are floating and therefore the output capacitor has no path to discharge. The LED current responds accurately with the PWM signal (see Figure 13). The output switches very quickly to the target current with minimal settling ringing and without being modulated by the PWM signal, and therefore minimizes any system disturbance.
FIGURE 10. DIMMING LINEARITY vs DUTY CYCLES ZOOM IN
The low level non-linearity effects at high frequency PWM dimming is also reflected in the efficiency measurements in Figure 11.
90 85 80 EFFICIENCY (%)
VOUT
LX
PWM/EN 75 70 65 60 55 50 0 5 10 15 ILED (mA) 20 3 LEDs VIN = 4V RSET = 4 L = 22H 25 30 ILED
VIN = 4V R1 = 4 L1 = 22H
FIGURE 13. PWM DIMMING AT 1kHz USING FBSW
Overvoltage Protection
The ISL97634 comes with overvoltage protection. The OVP trip points are at 14V, 18V and 26V for ISL97634IRT14Z, ISL97634IRT18Z and ISL97634IRT26Z respectively. The maximum numbers of LEDs and OVP threshold are shown in Table 1. When the device reaches the OVP, the LX stops switching, disabling the boost circuit until VOUT falls about 7% below the OVP threshold. At this point, LX will be allowed to switch again. The OVP event will not cause the device to shutdown. There are three OVP options so that the 3 LEDs application should use the 14V OVP device and the 7 LEDs application should use the 26V OVP device. An output capacitor that is
FIGURE 11. EFFICIENCY vs PWM DIMMING FREQUENCIES
Feedback Disconnect Switch
The ISL97634 functions properly without using the FBSW. However, the output capacitor will discharge during the PWM off time resulting in poor dimming linearity at low duty cycles. The output discharge effect can be seen in Figure 12. Moreover, the output is modulated by the PWM signal that may create interference to other systems.
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FN6264.3 March 7, 2008
ISL97634
only rated for the required voltage range can therefore be used, which will optimize the component costs in some cases.
TABLE 1. PART NO. ISL97634IRT14Z ISL97634IRT18Z ISL97634IRT26Z OVP 14V 18V 26V MAX NO. OF LEDS 3 4 7 MAX ILED 70mA 50mA 30mA
Compensation
The product of the output capacitor and the load create a pole while the inductor creates a right half plane zero. Both of these attributes degrade the phase margin but the ISL97634 has internal compensation network that ensures the device operates reliably under the specified conditions. The internal compensation and the highly integrated functions of the ISL97634 make it a design friendly device to be used in high volume, high reliability applications.
Shutdown
When PWM/EN is taken low the ISL97634 enters into the power-down mode where the supply current is reduced to less than 1A. The device resumes normal when the PWM/EN goes high.
Applications
Analog Dimming
Analog dimming is usually not recommended because of the brightness non-linearity at low levels dimming. However, some systems are EMI or noise sensitive that analog dimming may be more suitable than PWM dimming under those situations. The ISL97632 is part of the same family as the ISL97634 and has been designed with a serial interface to give access to 32 separate dimming levels. Alternatively analog dimming can be achieved by applying a variable DC voltage (VDim) at FB pin (see Figure 14) to adjust the LED current. As the DC dimming signal voltage increases above VFB, the voltages drop on R1 and R2 increase and the voltage drop on RSET decreases. Thus, the LED current decreases as shown in Equation 6:
V FB ( R 1 + R 2 ) - V Dim R 1 I LED = ------------------------------------------------------------------------R2 R
SET
Components Selection
The input capacitance is typically 0.22F. The output capacitor should be in the range of 0.22F to 1F. X5R or X7R type of ceramic capacitors of the appropriate voltage rating are recommended. When choosing an inductor, make sure the average and peak current ratings are adequate by using Equations 3, 4 and 5 (80% efficiency assumed):
I LED V OUT I LAVG = -------------------------------0.8 V IN 1 I LPK = I LAVG + -- I L 2 V IN ( V OUT - V IN ) I L = -------------------------------------------------L V OUT f OSC (EQ. 3)
(EQ. 6)
(EQ. 4)
If VDIM is taken below FB, the inverse will happen and the brightness will increase. The DC dimming signal voltage can be a variable DC voltage from a POT, a DCP (Digitally Controlled Potentiometer), or a DC voltage generated by filtering a high frequency PWM control signal.
L1 22H VIN 3.3V C1 1F VIN LX VOUT ISL97634 R1 PWM GND FB 3.3k C2 0.22F RSET 4.75 LEDs
(EQ. 5)
Where: * IL is the peak-to-peak inductor current ripple in Amps * L is the inductance in H * fOSC is the switching frequency, typically 1.45MHz The ISL97634 supports a wide range of inductance values (10H to ~82H). For lower inductor values or lighter loads, the boost inductor current may become discontinuous. For high boost inductor values, the boost inductor current will be in continuous mode. In addition to the inductor value and switching frequency, the input voltage, number of LEDs and the LED current also affects whether the converter operates in continuous conduction or discontinuous conduction mode. Both operating modes are allowed and normal. The discontinuous conduction mode yields lower efficiency due to higher peak current.
R2
VDim
FIGURE 14. ANALOG DIMMING CONTROL APPLICATION CIRCUIT
As brightness is directly proportional to LED currents, VDim may be calculated for any desired "relative brightness" (F) using Equation 7:
R1 R2 V Dim = ------ V FB 1 + ------ - F R1 R2 (EQ. 7)
Where F = ILED (dimmed)/ILED (undimmed).
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FN6264.3 March 7, 2008
ISL97634
These equations are valid for values of R1 and R2 such that both R1>>RSET and R2>>RSET. The analog dimming circuit can be tailored to a desired relative brightness for different VDim ranges using Equation 8.
[ ( V Dim_max - V FB ) * R 1 ] R 2 = ------------------------------------------------------------------[ V FB * ( 1 - F min ) ] (EQ. 8)
.
90
VS = 12V VS = 9V
EFFICIENCY (%)
85
80 VIN = 4V 7 LEDs L1 = 22H R1 = 4 fPWM 0 5 10 15 ILED (mA) 20 25 30
75
Where VDim_max is the maximum VDim voltage and Fmin is the minimum relative brightness (i.e., the brightness with VDim_max applied). i.e., VDim_max = 5V, Fmin = 10% (i.e., 0.1), R2 = 189k i.e., VDim_max = 1V, Fmin = 10% (i.e., 0.1), R2 = 35k
70
FIGURE 16. EFFICIENCY IMPROVEMENT WITH 9 AND 12V INPUTS
8 LEDs Operation
For medium size LCDs that need more than 7 low power LEDs for backlighting, such as a portable media player or automotive navigation panel displays, the voltage range of the ISL97634 is not sufficient. However, the ISL97634 can be used as an LED controller with an external protection MOSFET connected in cascode fashion to achieve higher output voltage. A conceptual 8 LEDs driver circuit is shown in Figure 17. A 60V logic level NChannel MOSFET is configured such that its drain ties between the inductor and the anode of Schottky diode, its gate ties to the input, and its source ties to the ISL97634 LX node connecting to the drain of the internal switch. When the internal switch turns on, it pulls the source of M1 down to ground and LX conducts as normal. When the internal switch turns off, the source of M1 will be pulled up by the follower action of M1, limiting the maximum voltage on the ISL97634 LX pin to below VIN, but allowing the output voltage to go much higher than the breakdown limit on the LX pin. The switch current limit and maximum duty cycle will not be changed by this setup, so input voltage will need to be carefully considered to make sure that the required output voltage and current levels are achievable. Because the source of M1 is effectively floating when the internal LX switch is off, the drain-to-source capacitance of M1 may be sufficient to capacitively pull the node high enough to break down the gate oxide of M1. To prevent this, VOUT should be connected to VIN, allowing the internal Schottky diode to limit the peak voltage. This will also hold the VOUT pin at a known low voltage, preventing the built in OVP function from causing problems. This OVP function is effectively useless in this mode as the real output voltage is outside its intended range. If the user wants to implement their own OVP protection (to prevent damage to the output capacitor), they should insert a zener diode from VOUT to the FB pin. In this setup, it would be wise not to use the FBSW to FB switch, as otherwise, the zener diode will have to be a high power one capable of dissipating the entire LED load power. Then the LED stack can then be connected directly to the sense resistor via a 10k resistor to FB. A zener can be placed from VOUT to the FB pin allowing an overvoltage event to pull-up on FB with a low breakdown current (and thus low power zener diode) as a result of the 10k resistor.
Efficiency Improvement
Figure 1 shows the efficiency measurements during PWM operation. The choice of the inductor has a significant impact on the power efficiency. As shown in Equation 4, the higher the inductance, the lower the peak current, therefore, the lower the conduction and switching losses. On the other hand, it has also a higher series resistance. Nevertheless, the efficiency improvement effect by lowering the peak current is greater than the resistance increases with larger value of inductor. Efficiency can also be improved for systems that have high supply voltages. Since the ISL97634 can only supply from 2.4V to 5.5V, VIN must be separated from the high supply voltage for the boost circuit as shown in Figure 15 and the efficiency improvement is shown in Figure 16.
C3 0.22F D1 Vs = 12V C1 1F L1 1 22H D3 D4 VIN LX D5 D6 VOUT ISL97634 FBSW FB PWM/EN GND R1 4 2 D2
VIN = 2.7V TO 5.5V C2 0.1F
FIGURE 15. SEPARATE HIGH INPUT VOLTAGE FOR HIGHER EFFICIENCY OPERATION
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FN6264.3 March 7, 2008
ISL97634
L1 2.2 M1 VIN C2 0.1F VOUT LX ISL97634 FBSW FB D5 R1 6.3 D6 D7 D8 D0 10BQ100 C3 4.7F D1 D2 D3 D4
VIN = 2.7V TO 5.5V C1 1F
1
2
FQT13N06L SK011C226KAR
PWM/EN GND
The SEPIC works as follows; assume the circuit in Figure 18 operates normally when the ISL97634 internal switch opens and it is in the PWM off state. After a short duration where few LC time constants elapsed, the circuit is considered in the steady-state within the PWM off period that L1 and L2 are shorted. VB is therefore shorted to the ground and C3 is charged to VIN with VA = VIN. When the ISL97634 internal switch closes and the circuit is in the PWM on-state, VA is now pulled to ground. Since the voltage in C3 cannot be changed instantaneously, VB is shifted downward and becomes -VIN. The next cycle when the ISL97634 switch opens, VB boosts up to the targeted output like the standard boost regulator operation, except the lowest reference point is at -VIN. The output is approximated in Equation 9:
D V OUT = V IN ----------------(1 - D) (EQ. 9)
FIGURE 17. CONCEPTUAL 8 LEDs HIGH VOLTAGE DRIVER
SEPIC Operation
For applications where the output voltage is not always above the input voltage, a buck or boost regulation is needed. A SEPIC (Single Ended Primary Inductance Converter) topology, shown in Figure 18, can be considered for such an application. A single cell Li-ion battery operating a cellular phone backlight or flashlight is one example. The battery voltage is between 2.5V and 4.2V, depending on the state of charge. On the other hand, the output may require only one 3V to 4V medium power LED for illumination because the light guard of the backlight assembly is optimized for cost efficiency trade-off reason. In fact, a SEPIC configured LED driver is flexible enough to allow the output to be well above or below the input voltage, unlike the previous example. Another example is when the number of LEDs and input requirements are different from platform to platform, a common circuit and PCB that fit all the platforms in some cases may be beneficial enough that it outweighs the disadvantage of adding additional component cost. L1 and L2 can be a coupled inductor in one package.
VIN = 2.7V TO 5.5V 1 L1 2 22H C1 1F VIN C2 0.1F LX VOUT ISL97634 FBSW FB SDIN GND R1 1 VA C3 1F VB D0 C4 L2 22H 0.22F
where D is the on-time of the PWM duty cycle. The convenience of SEPIC comes with some trade-off in addition to the additional L and C costs. The efficiency is usually lowered because of the relatively large efficiency loss through the Schottky diode if the output voltage is low. The L2 series resistance also contributes additional loss. Figure 19 shows the efficiency measurement of a single LED application as the input varies between 2.7V and 4.2V. Note VB is considered the level-shifted LX node of a standard boost regulator. The higher the input voltage, the lower the VB voltage will be during PWM on period. The result is that the efficiency will be lower at higher input voltages because the SEPIC has to work harder to boost up to the required level. This behavior is the opposite to the standard boost regulator's and the comparison is shown in Figure 19.
76 VIN = 2.7V EFFICIENCY (%) 72 VIN = 4.2V
68 1 LED L1 = L2 = 22H C3 = 1F R1 = 4.7 60 0 5 10 ILED (mA) 15 20
64
D1
FIGURE 19. EFFICIENCY MEASUREMENT OF A SINGLE LED SEPIC DRIVER
PCB Layout Considerations
The layout is very important for the converter to function properly. RSET must be located as close as possible to the FB and GND pins. Longer traces to the LEDs are acceptable. Similarly, the supply decoupling cap and the output filter cap should be as close as possible to the VIN and VOUT pins. The heat of the IC is mainly dissipated through the thermal pad of the package. Maximizing the copper area connected to this pad if possible. In addition, a solid ground plane is always helpful for the EMI performance.
FIGURE 18. SEPIC LED DRIVER
The simplest way to understand SEPIC topology is to think about it as a boost regulator where the input voltage is level shifted downward at the same magnitude and the lowest reference level starts at -VIN rather than 0V.
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FN6264.3 March 7, 2008
ISL97634 Thin Dual Flat No-Lead Plastic Package (TDFN)
2X 0.15 C A A D 2X 0.15 C B
L8.2x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A
E
MIN 0.70 -
NOMINAL 0.75 0.20 REF
MAX 0.80 0.05
NOTES -
A1 A3 b D
6 INDEX AREA B
0.20
0.25 2.00 BSC
0.32
5,8 -
TOP VIEW
D2 E
// 0.10 C
1.50
1.65 3.00 BSC
1.75
7,8 -
E2
A 0.08 C
1.65
1.80 0.50 BSC
1.90
7,8 -
e k L N 0.20 0.30
C SEATING PLANE
SIDE VIEW
A3
0.40 8 4
0.50
8 2 3 Rev. 0 6/04
D2 (DATUM B) 1 2 D2/2
7
8
Nd NOTES:
6 INDEX AREA (DATUM A)
NX k
1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D.
E2 E2/2
4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
NX L N N-1 NX b 8 e (Nd-1)Xe REF. BOTTOM VIEW (A1) NX (b) 5 SECTION "C-C" CC e FOR EVEN TERMINAL/SIDE TERMINAL TIP L C L 5 0.10 M C AB
7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN6264.3 March 7, 2008

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